个人简历 cv

教育经历、工作经历、研究方向与代表成果。 Education, professional experience, research directions, and selected publications.

个人简介

姜伟雄

姜伟雄

同济大学电子与信息工程学院助理教授

姜伟雄，同济大学电子与信息工程学院助理教授。2017 年获哈尔滨工业大学电磁场与无线技术专业学士学位，2022 年获中国科学院大学微电子学与固体电子学专业博士学位。

博士毕业后先后任职于华为海思图灵架构部与蔚来汽车自动驾驶芯片开发部，从事 GPU 与 NPU 的架构定义、关键模块论证、方案设计、RTL 开发及性能建模等工作，系统覆盖数字芯片前端核心岗位中的架构、建模与设计三大方向。

近五年来在 TCAD、TCAS-I、TCAS-II、TVLSI、DAC 等集成电路领域高水平期刊与会议上发表论文十余篇，其中以第一作者或通讯作者发表 6 篇，拥有国际授权专利 2 项。

AI 处理器及软件栈设计 端侧大语言模型处理器 架构探索与软硬件协同设计

基本信息

姓名 姜伟雄
职称 助理教授
学科 电子科学与技术
专业 微电子
研究方向 AI 处理器及软件栈设计
电子邮件 jiangweixiong@tongji.edu.cn
联系电话 17612153732
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教育经历

  • 2022
    中国科学院大学，微电子学与固体电子学，博士
  • 2017
    哈尔滨工业大学，电磁场与无线技术，学士

工作经历

  • 2025-至今
    同济大学电子与信息工程学院，助理教授
    • 2025 年 7 月加入同济大学。
    • 围绕 AI 处理器及软件栈设计开展教学与科研工作。
  • 2022-2025
    华为海思图灵架构部、蔚来汽车自动驾驶芯片开发部
    • 从事 GPU 与 NPU 的架构定义、关键模块论证、方案设计、RTL 开发及性能建模。
    • 在产业环境中系统积累了数字芯片前端在架构、建模与设计三大方向的实践经验。

研究方向

  • 端侧大语言模型处理器（LPU）全栈设计
    • 推理框架设计
    • 算子设计与优化
    • 架构设计与探索
    • 微架构设计与优化
    • 软硬件协同设计

指导理念

  • 方法论先行，理论与实践螺旋上升
    • 进组后首先系统学习一套贯穿代码编写、论文写作、方案设计的通用方法论，再通过日常科研工作将其内化。
  • 面向产业需求，培养全栈能力
    • 业务能力覆盖 LPU 全栈理解，包括推理框架、算子设计与优化、架构设计与探索、微架构设计与优化、软硬件协同设计。
    • 通用低阶能力包括 Verilog、C++、UVM 芯片验证；通用高阶能力包括抽象、演绎、系统思维与结构化表达。
  • 有组织科研，集中力量办大事
    • 课题组围绕 LPU 全栈开展研究，各位同学共同维护一个科研平台，并围绕关键模块深度优化。
  • 渐进式培养，因材施教
    • 调试代码或做 UVM 验证 → 独立编写 C++/Verilog 代码 → 撰写小模块方案 → 撰写中模块方案 → 撰写大模块方案 → 主导另一核心模块。

沟通机制

  • 每周一次全体组会对齐进度。
  • 日常不定期技术组会，包括方案串讲、方案讨论、代码检视。
  • 保持一对一答疑，确保问题能够及时解决。

实习与就业

  • 就业辅导
    • 包括简历修改、模拟面试等。
    • 表现优秀者可获大厂核心部门内推机会。
  • 实习安排
    • 课题组与两家芯片大厂建有实习生合作关系，表现优秀者可直接内推。
    • 未满足毕业要求前原则上不允许自行外出实习；满足毕业要求后充分放行。

荣誉与奖项

  • 2021
    • DAC-SDC'21 冠军（神经网络加速器领域 Top 竞赛，全球 116 支队伍，所有指标均第一）
    • 中国电子学会集成电路奖学金一等奖
  • 2020
    • DAC-SDC'20 亚军

代表论文

  • 2025
    • Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang*, Yajun Ha*: RefSCAT-2.0: Formal Verification of Large-Scale Optimized Multipliers via Quantum-Inspired Ant Colony Optimization-Based Reference Generation. IEEE TCAD, 2025.
    • Qi Deng, Hao Sun, Yuhao Shu, Jianzhong Xiao, Weixiong Jiang, Hui Wang, Yajun Ha: An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search. ACM TRETS, 2025.
    • Shijie Meng, Qi Deng, Weixiong Jiang, Jinjie Huang, Hao Sun, Yajun Ha: An FPGA-Based Real-Time Loop Closure Detection Framework With Ultra-Fast Descriptor Generator. IEEE TCAS-I, 2025.
    • Shen Zhang, Bin Ning, Guangyao Yan, Xinzhe Liu, Weixiong Jiang, Yajun Ha: QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models. IEEE TCAD, 2025.
    • Junge Xu, Fan Zhang, Wenguang Jin, Kun Yang, Zeke Wang, Weixiong Jiang, Yajun Ha: A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators. IEEE TCAD, 2025.
    • Jingjin Li, Weixiong Jiang, Yuting He, Qingyu Yang, Anqi Gao, Yajun Ha, Ender Özcan, Ruibin Bai, Tianxiang Cui, Heng Yu: FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in Embedded Systems. IEEE Transactions on Computers, 2025.
  • 2023
    • Weixiong Jiang, Heng Yu, Yajun Ha: A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA. IEEE TCAD, 2023.
    • Weixiong Jiang, Heng Yu, Fupeng Chen, Yajun Ha: AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA. IEEE TCAD, 2023.
  • 2022
    • Weixiong Jiang, Heng Yu, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha: FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. IEEE TVLSI, 2022.
    • Fupeng Chen, Heng Yu, Weixiong Jiang, Yajun Ha: Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices. IEEE TCAD, 2022.
    • Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha: A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. IEEE TVLSI, 2022.
  • 2021
    • Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha: TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. DAC, 2021.
    • Hongtu Zhang, Yuhao Shu, Weixiong Jiang, Zihan Yin, Wenfeng Zhao, Yajun Ha: A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications. IEEE TCAS-II, 2021.
  • 2020
    • Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha: An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. ISCAS, 2020.
    • Hao Sun, Xinzhe Liu, Qi Deng, Weixiong Jiang, Shaobo Luo, Yajun Ha: Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles. IEEE TCAS-II, 2020.

Profile

Weixiong Jiang

Weixiong Jiang

Assistant Professor, College of Electronics and Information Engineering, Tongji University

Weixiong Jiang is an Assistant Professor at the College of Electronics and Information Engineering, Tongji University. He received his B.Eng. in Electromagnetic Field and Wireless Technology from Harbin Institute of Technology in 2017 and his Ph.D. in Microelectronics and Solid State Electronics from the University of Chinese Academy of Sciences in 2022.

After completing his doctorate, he worked in Huawei HiSilicon's Turing Architecture Department and NIO's autonomous driving chip division, focusing on GPU and NPU architecture definition, key module analysis, solution design, RTL development, and performance modeling across the major front-end roles of digital chip design.

Over the past five years, he has published more than ten papers in leading integrated-circuit journals and conferences such as TCAD, TCAS-I, TCAS-II, TVLSI, and DAC, including six papers as first or corresponding author, and holds two granted international patents.

AI processors and software stacks Edge large language model processors Architecture exploration and software-hardware co-design

Basic Information

Name Weixiong Jiang
Title Assistant Professor
Discipline Electronic Science and Technology
Major Microelectronics
Research Area AI processor and software stack design
Email jiangweixiong@tongji.edu.cn
Phone 17612153732
Lab Website
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Education

  • 2022
    Ph.D. in Microelectronics and Solid State Electronics, University of Chinese Academy of Sciences
  • 2017
    B.Eng. in Electromagnetic Field and Wireless Technology, Harbin Institute of Technology

Professional Experience

  • 2025-present
    Assistant Professor, College of Electronics and Information Engineering, Tongji University
    • Joined Tongji University in July 2025.
    • Conducts teaching and research on AI processors and software stacks.
  • 2022-2025
    Huawei HiSilicon Turing Architecture Department and NIO Autonomous Driving Chip Division
    • Worked on GPU and NPU architecture definition, key module analysis, solution design, RTL development, and performance modeling.
    • Built systematic industry experience across architecture, modeling, and design in digital chip front-end development.

Research Directions

  • End-to-end design of edge large language model processors (LPU)
    • Inference framework design
    • Operator design and optimization
    • Architecture design and exploration
    • Microarchitecture design and optimization
    • Software-hardware co-design

Mentoring Philosophy

  • Methodology first, with theory and practice reinforcing each other
    • Students first learn a general methodology that spans coding, paper writing, and technical proposal design, then internalize it through daily research work.
  • Industry-oriented training with full-stack capability
    • Research training covers the full LPU stack, including inference frameworks, operator design and optimization, architecture exploration, microarchitecture optimization, and software-hardware co-design.
    • Foundational skills include Verilog, C++, and UVM verification; higher-level skills emphasize abstraction, deduction, systems thinking, and structured communication.
  • Organized research with shared infrastructure
    • The group develops research around a shared LPU full-stack platform, with students jointly maintaining the platform and deeply optimizing key modules.
  • Progressive and personalized training
    • Debugging or UVM verification -> independent C++ or Verilog development -> small-module proposal writing -> medium-module proposal writing -> large-module proposal writing -> leadership of another core module.

Communication Mechanism

  • A full group meeting is held every week to align progress.
  • Additional technical meetings are organized as needed for proposal walkthroughs, design discussions, and code reviews.
  • One-on-one discussions are maintained to resolve issues in a timely manner.

Internships and Career Development

  • Career support
    • Includes resume revision and mock interviews.
    • Outstanding students may receive referrals to core teams in major companies.
  • Internship arrangement
    • The group maintains internship partnerships with two major chip companies, and strong students can be directly referred.
    • In principle, students are not encouraged to take outside internships before meeting graduation requirements; after those requirements are met, internship participation is fully supported.

Honors and Awards

  • 2021
    • DAC-SDC'21 Champion (top accelerator competition in neural-network hardware; 116 teams worldwide; ranked first on every metric)
    • First Prize, Integrated Circuit Scholarship of the Chinese Institute of Electronics
  • 2020
    • DAC-SDC'20 Runner-up

Selected Publications

  • 2025
    • Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang*, Yajun Ha*: RefSCAT-2.0: Formal Verification of Large-Scale Optimized Multipliers via Quantum-Inspired Ant Colony Optimization-Based Reference Generation. IEEE TCAD, 2025.
    • Qi Deng, Hao Sun, Yuhao Shu, Jianzhong Xiao, Weixiong Jiang, Hui Wang, Yajun Ha: An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search. ACM TRETS, 2025.
    • Shijie Meng, Qi Deng, Weixiong Jiang, Jinjie Huang, Hao Sun, Yajun Ha: An FPGA-Based Real-Time Loop Closure Detection Framework With Ultra-Fast Descriptor Generator. IEEE TCAS-I, 2025.
    • Shen Zhang, Bin Ning, Guangyao Yan, Xinzhe Liu, Weixiong Jiang, Yajun Ha: QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models. IEEE TCAD, 2025.
    • Junge Xu, Fan Zhang, Wenguang Jin, Kun Yang, Zeke Wang, Weixiong Jiang, Yajun Ha: A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators. IEEE TCAD, 2025.
    • Jingjin Li, Weixiong Jiang, Yuting He, Qingyu Yang, Anqi Gao, Yajun Ha, Ender Özcan, Ruibin Bai, Tianxiang Cui, Heng Yu: FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in Embedded Systems. IEEE Transactions on Computers, 2025.
  • 2023
    • Weixiong Jiang, Heng Yu, Yajun Ha: A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA. IEEE TCAD, 2023.
    • Weixiong Jiang, Heng Yu, Fupeng Chen, Yajun Ha: AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA. IEEE TCAD, 2023.
  • 2022
    • Weixiong Jiang, Heng Yu, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha: FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. IEEE TVLSI, 2022.
    • Fupeng Chen, Heng Yu, Weixiong Jiang, Yajun Ha: Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices. IEEE TCAD, 2022.
    • Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha: A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. IEEE TVLSI, 2022.
  • 2021
    • Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha: TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. DAC, 2021.
    • Hongtu Zhang, Yuhao Shu, Weixiong Jiang, Zihan Yin, Wenfeng Zhao, Yajun Ha: A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications. IEEE TCAS-II, 2021.
  • 2020
    • Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha: An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. ISCAS, 2020.
    • Hao Sun, Xinzhe Liu, Qi Deng, Weixiong Jiang, Shaobo Luo, Yajun Ha: Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles. IEEE TCAS-II, 2020.